Scalable Hardware Architecture for Montgomery Inversion Computation in Dual-Field

摘要：

Computing the inverse of a number in finite fields GF(p) or GF(2n) is equally important for cryptographic applications. A novel scalable and unified architecture for a Montgomery inversion hardware that operates in both GF(p) and GF(2n) is proposed. The scalable design is the novel modification performed on the fixed hardware to make it occupy a small area and operate with better or similar speed, and it takes less number of clock cycle as the fixed datapath is large and can also achieve high clock frequency. Finally this work has been verified by modeling it in Verilog-HDL, implementing it under 0.18μm CMOS technology. The reault indicates that our work has advanced performance than other works.

关键词： Montgomery inversion algorithm Scalable hardware architecture FPGA ASIC

作者: Dai Zi-bin Qin Fan Yang Xiao-hui

作者单位: Institute of electronic technology, Information Engineering University ZhengZhou, China

会议类型: 国际会议

会议名称: 2009 WASE International Conference on Information Engineering(2009年国际信息工程会议)(ICIE 2009)

会议地点: 太原

会议语种:英文

页码: 865-868

在线出版日期: 2009-07-10（万方平台首次上网日期，不代表论文的发表时间）