Design and Implementation of Reconfigurable Security Hash Algorithms based on FPGA
Today, security is a topic which attacks the great interest of researchers. Many encryption algorithms have been investigated, and developed in the last years. Hash functions are important security primitives used for authentication and data integrity. The reconfigurable cryptographic chip is an integrated circuit that is designed by means of the method of reconfigurable architecture, and is used for encryption and decryption. It can implement many different cipher algorithms flexibly and quickly, and be used in many fields. This work is related to hash functions KPGA implementation. Five different hash functions SHA-1, SHA-224, SHA-256, SHA-384 and SHA-S12 are studied. A reconfigurable architecture is proposed for the implementation of all of them in the same hardware module. Finally, it gives the implementation results based on the FPGA of the family of Stratix II of Altera Corporation. The proposed system reaches throughput values equal to 727.853Mbps for SHA-41, 909.816Mbps for SHA-224/256, and 1.456Gbps for SHA-384/S12 respectively.
Reconfigurable cryptographic chip SHA-1/224/256/384/S12 FPGA
LI Miao XU Jinfu YANG Xiaohui YANG Zhifeng
Institute of Electronic Technology, Information Engineering University, ZhengZhou, China
国际会议
2009 WASE International Conference on Information Engineering(2009年国际信息工程会议)(ICIE 2009)
太原
英文
1040-1043
2009-07-10（万方平台首次上网日期，不代表论文的发表时间）