A NEW DYNAMIC RECONFIGURABLE TECHNOLOGY TO REDUCE POWER DISSIPATION

摘要：

This paper first describes the reconfigurable technology related research field and the research significance on SoC Cache. Then gives the collectivity structure of SoC2000 , processor reconstruct, double nuclear communication model and interlinkage style, induct scheme, synchronization method and principle and subordinate CPU nuclear clock mutual close. This new technology can improve batches rate of CMOS chips.

关键词： Power Dissipation Soc Reconfigurable Technology CMOS Chip

作者: YIL-EI WANG TAO LI CHAN-JUAN LIU HONG-GUO LI

作者单位: The Department of Computer Science & Technology, Lu Dong University, Yantai 264025,China The Network Center, Lu Dong University, Yantai 264025,China

会议类型: 国际会议

会议名称: 2008 International Conference on Machine Learning and Cybernetics(2008机器学习与控制论国际会议)

会议地点: 昆明

会议语种:英文

页码: 2202-2205

在线出版日期: 2008-07-12（万方平台首次上网日期，不代表论文的发表时间）