IMPROVED MULTIPLIER OF CSD USED IN DIGITAL SIGNAL PROCESSING

摘要：

Multiplication is the basic operation unit in digital signal processing. Its speed determines the performance of the system, such as CUP, DSP, digital filter and so on. CSD (Canonical Signed-digit) code is characterized by low resource occupation, high efficiency and high parallel speed. It can efficiently reduce the operation load and time consumption. In addition, this design integrates the Wallace tree addition and carry look-ahead addition with the operation unit of CSD, the former can reduce the addition amount, then the latter improved the operation speed, thus which has further improved the performance of the multiplication operation. At last, we realized the verification by FPGA.

关键词： CSD Wallace tree adder carry look-ahead adder FPGA

作者: LEI CHEN XIAO-YAN TIAN XIAO-JUN ZHAO

作者单位: College of Electronic and Information Engineering, Hebei University, Baoding 071002, China

会议类型: 国际会议

会议名称: 2008 International Conference on Machine Learning and Cybernetics(2008机器学习与控制论国际会议)

会议地点: 昆明

会议语种:英文

页码: 2905-2908

在线出版日期: 2008-07-12（万方平台首次上网日期，不代表论文的发表时间）