A NEW FABRIC OF RECONFIGURABLE FFT PROCESSOR FOR HIGH-SPEED AND LOW-COST SYSTEM

摘要：

A high-speed reconflgurable FFT architecture based on FPGA is proposed in this paper. The system can be configured as 32, 64,128, 256, 512 and 1024-point FFT using simplified method to control. It has been synthesized in Xilinx Virtex2p FPGA and post-simulated. Compared with Xilinx FFT IP Core with the same function ,this FFT fabric proposed has saved almost 8％～9％ (equivalent gates) in resources consumption while increased nearly 6％～25％ in clock frequency and decreased 56-116 cycles of delays from first input data to the first result data, indicating high computing efficiency. On the other hand, power consumption is also slightly fewer than the IP Cores. The fabric we presented in this paper is suitable for use in digital signal process with high-speed and low-cost.

关键词： Reconfigurable FFT FPGA

作者: HUAN LIU WEI PAN SHUI-SHENG LIN

作者单位: School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu, 610054, P.R.China

会议类型: 国际会议

会议名称: 2008 International Conference on Machine Learning and Cybernetics(2008机器学习与控制论国际会议)

会议地点: 昆明

会议语种:英文

页码: 3525-3529

在线出版日期: 2008-07-12（万方平台首次上网日期，不代表论文的发表时间）