HARDWARE IMPLEMENTATION OF RECURRENT S_CMAC_GBF BASED ON FPGA
This study is to design and develop the hardware structure of Recurrent S CMACGBF 3, and to implement and test the hardware structure by using FPGA chip. S_CMAC_GBF has the same learning convergence characteristic as in CMACGBF, but with stronger system accuracy. The learning structure of recurrent enables SCMAC GBF with the ability to solve dynamic system or time relevant problem. Although S_CMAC_GBF and Recurrent SCMAC GBF have outstanding learning performances and applications in static and dynamic systems, both are restricted to the huge computer size and input/output speed, therefore, it is hard to expand their applications. This study reduces the system size to IC grade and increase the processing speed from m sec to μ sec. And there are two temporal relevant examples are employed to demonstrate the performance of the hardware implementation.
Recurrent S_CMAC_GBF FPGA Temporal Relevant Hardware Implementation
CHING-TSAN CHIANG YU-BIN LENT CHIA-YEN HSIEH
Electrical Engineering Department, Ching Yun University, Jung-Li 320, Taiwan
国际会议
2008 International Conference on Machine Learning and Cybernetics(2008机器学习与控制论国际会议)
昆明
英文
3845-3850
2008-07-12（万方平台首次上网日期，不代表论文的发表时间）