Ant Colony Optimization for Test Scheduling of System on Chip
Test scheduling is one of major tasks in the test of system on chip, which is a process that determines the test start and finishing time of every core in the system on chip such that the overall test time is minimized. A new test scheduling approach based on chaotic ant colony algorithm is presented in this paper. First of all, the optimization model of test scheduling is presented, the model uses the information such as the scale of test sets of both cores and user defined logic, and the bits width of the test access mechanism. Secondly, an approach based on chaotic ant colony algorithm is proposed to solve the optimization model of test scheduling. The chaotic maps are added to ant colony algorithm in order to improve the computation performances and to void the algorithm search being trapped in local optimums. The test structure optimization for system on chip is also studied. Experimental results on a lot of benchmark circuits show that the proposed approach in this paper can be used to solve test scheduling problems in short computational time.
System on chip test scheduling embedded core ant colony algorithms chaotic maps
Chen Ling Pan Zhongliang Zhang Guangzhao
Department of Electronics, South China Normal University, Guangzhou 510006, China Department of Electronics and Communications, Sun Yat-sen University, Guangzhou 510275, China
国际会议
2008 Sino-European Workshop on Intelligent Robots and Systems(SEIROS08)(第一届中欧智能系统及机器人国际学术研讨会)
重庆
英文
1-7
2008-12-11（万方平台首次上网日期，不代表论文的发表时间）