The Future of CMOS Scaling Parasitics Engineering and Device Footprint Scaling

摘要：

We explore options for device scaling beyond the conventional scaling path. We examine the role of the parasitic capacitance for determining the performance of future one-dimensional FETs. We also explore a possible device scaling path that focuses on aggressive scaling of the contacted gate pitch,which provides performance improvements at both the device and circuit level.

作者: H.-S.Philip Wong Lan Wei Jie Deng

作者单位: Dept of Electrical Engineering and Center for Integrated Systems,Stanford University,Stanford,CA 943 Dept of Electrical Engineering and enter for Integrated Systems,Stanford University,Stanford,CA 9430

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 21-24

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）