Road-blocks to Tera-level Nanoelectronics

摘要：

The national program for Tera-level Nanodevices (TND) serves as a frontier research resource to a broad range of nanoscale electronics areas.Outstanding nanoscale devices have been achieved and are being further developed using core technologies such as fast nanoscale molecular assembly, damage-free nano-etch process with a neutral beam and nano-rod and particle formation technology.Sub-30 ran scale nonvolatile memory arrays have been demonstrated by changing structures and materials.Using high quality heterojunction epitaxial growth technology, ultra high speed HEMT devices have been demonstrated with cut-off frequencies of approximately 610 GHz corresponding to gate length of 15 run.Additionally, single electron transistor logic circuits have been extended to multi-valued static random access memory applications.

作者: Jo-Won Lee Moonkyung Kim

作者单位: The National Program for Tera-level Nano Devices, 39-1, Hawolgok-ding, Seoul, Korea School of Electrical and Computer Engineering, Cornell University, New York, USA

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 37-40

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）