CMOS Gate Height Scaling

摘要：

The work addresses benefits and performance impacts resulted from CMOS gate height reduction. The experiment shows that capacitance arising between the CMOS source/drain contact and the gate electrode decreases about linearly as the gate height scales down. The result also shows that stress liner techniques continue providing strong performance enhancement for CMOS as the gate height scales from 100nm to 50nm.For ring oscillators built with 45nm node CMOS technology, the capacitance benefit associated with gate height reduction from 100nm to 80nm improves the circuit speed by ～3%.

作者: Zhibin Ren K.T.Schonenberg V.Ontalus I.Lauer S.A.Butt

作者单位: IBM Systems & Technology Group, IBM Semiconductor Research & Development Center, HopewellJunction, N IBM Semiconductor Research and Development Center, T.J.Watson Research Center, Yorktown Heights, NY

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 41-42

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）