Air Spacer MOSFET Technology for 20nm Node and Beyond

摘要：

Two types of air spacer technologies are proposed and TCAD simulation is used to construct 20nm-gate transistor.One is non-SAC (Self Aligned Contact) process with air spacer. It is compared with nitride-spacer and oxide-spacer transistors representing the two extremes of conventional spacer technologies.With 10nm air spacers, the CMOS inverter delay is reduced by 45% and 30% compared to the nitride-spacer and oxide-spacer technologies respectively.Furthermore, the switching energy (power consumption) is reduced by 46% and 33% respectively. The other is SAC process with air spacer.3D mixed mode simulation shows that the 35% area benefit can be retained while improving the speed and switching energy by 75% to be 10% better than a non-SAC device.

作者: Jemin Park Chenming Hu

作者单位: Department of Electrical Engineering and Computer Science University of California, Berkeley, CA 94720, USA

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 53-56

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）