Strain Influence on Analog Performance of Single-Gate and FinFET SOI nMOSFETs
This work studies the analog performance of uniaxially and biaxially strained single-gate fully depleted SOI nMOSFETs and standard and strained Si (sSOI) ntype triple-gate FinFETs with high-K dielectrics and TiN gate material. The analysis is performed focusing on some important analog figures of merit such as transconductance, Early voltage, output conductance and intrinsic voltage gain. It is shown that for single-gate devices the use of any kind of strain promotes the improvement of most analog parameters, resulting in a better or at least not worsen gain than for its unstrained counterpart.However for FinFETs devices, it is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas an increase of the channel length degrades the Early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones.Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect.Only for wider and long FinFETs the effect of strain is favorable to both gm and gD, resulting in a larger intrinsic voltage gain than in standard FinFETs.
Joao Antonio Martino Marcelo Antonio Pavanello Eddy Simoen Cor Claeys
LSI/PSI/USP, University of Sao Paulo, Brazil LSI/PSI/USP, University of Sao Paulo, Brazil DEE, Centra Universitario da FEI,Brazil IMEC, Leuven, Belgium IMEC, Leuven, Belgium E.E.Dept, KU Leuven, Belgium
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
84-87
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）