Stress Engineering for 32nm CMOS Technology Node

摘要：

Various aspects of the influence of scaling on stress engineering for 32nm node are reviewed.Numerical simulations of width effect of embedded SiGe (e-SiGe) induced stress and the physical mechanism of stress memorization technique (SMT) are presented in this paper.A novel SMT scheme to further improve performance of PMOSFET is reviewed and demonstrated using numerical simulations.

作者: Jeff Wu Xin Wang

作者单位: Texas Instruments Inc., Dallas, TX, USA

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 113-116

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）