SMT and enhanced SPT with Recessed SD to Improve CMOS Device Performance

摘要：

For nFET, mechanism of Stress Memorization Technique (SMT) has been investigated. It showed, for the first time, that SMT effect on nFET improvement is not only from poly gate, but also from Si at extension area.For pFET, a novel low cost technique to improve device performance by enhanced Stress Proximity Technique (eSPT) with Recessed SD (ReSD) has been demonstrated for the first time.pFET performance improvement of 40% was demonstrated with eSPT.15% improvement in ring delay has been demonstrated with optimized eSPT.

作者: S.Fang M.Belyansky J.Yari Z.Luo J.Li Y.Wang B.Greene H.Ng Y.Li H.Shang E.Maciejewski S.S.Tan M.Yang R.Divakaruni E.Leobandung JJagannathan J.Yuan Q.Liang T.Dyer R.Robinson I.Liu J.J.Kim B.Zuo

作者单位: IBM Semiconductor Research and Development Center (SRDC), Hopewell Junction, NY 12533 Infineon Technologies AG Chartered Semiconductor Manufacturing Samsung Electronics Co., Ltd

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 117-120

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）