Strained Silicon Dynamic Threshold Voltage MOSFETs for Low Voltage and Ultra High Speed CMOS circuits

摘要：

With the rapid development of integrated circuit industry, the demand for low voltage operation and high speed of digital CMOS circuits is becoming inevitable. The Dynamic Threshold voltage (DT) technique emerged to extend lower bound of power supply, while the strained silicon technique stands out as a cost-effective way to improve circuit speed. In this work, the combination of Dynamic Threshold voltage technique with strained silicon technique is explored and demonstrated on bulk silicon substrate. The strained silicon DT NMOS exhibit a lower subthreshold swing of 66m V/dec and a remarkably higher saturate drain current of 10.9X at Vds=0.5V, compared to standard strained silicon NMOS.As the result of these improvements, the strained silicon DT-CMOS inverter remains eligible with the power supply voltage down to 0.3V.

关键词： low voltage dynamic threshold voltage strained silicon CMOS

作者: Weiying Gu Renrong Liang Mei Zhao Jun Xu

作者单位: Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics, Tsinghua University, Beijing 100084, P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 134-137

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）