Source/Drain junction integration issues in submicron Ge MOSFETs
Source/Drain (S/D) engineering in Ge MOSFETs is a complex interplay of various factors,including ion implantation and annealing conditions,electrical activation,the defectiveness of the starting substrate and the contact technology.Some of these aspects will be covered in the following manuscript. It is shown that the formation of highly n-type doped S/D regions suffers from a concentration-enhanced diffusion and an activation ceiling at 5-6×1019 cm-3,which is insufficient for the (sub)-22 nm CMOS node. Techniques to reduce the enhanced diffusion,like co-implantation with N or C or ultra-fast annealing are discussed,but at the same time do not seem to break the activation barrier. The formation of highly B-doped p+junctions,on the other hand,does not suffer from enhanced diffusion,while active concentrations in the low 1020 cm-3 range can be achieved with standard Rapid Thermal Annealing.Only for low-energy B implants typical for extensions,evidence of interstitial-mediated Transient-Enhanced Diffusion (TED) is obtained. The main issue for p+S/D-junctions appears to be the fine-tuning of the halo implantation. It is shown that the junction leakage current increases quasi-exponentially with higher halo doping concentration. It is,finally,shown that the implementation of a NiGe contact metallization can give rise to a higher perimeter leakage current,associated with the formation of voids.
E.Simoen A.Satta G.Eneman D.P.Brunco B.De Jaeger K.Opsomer M Meuris C.Claeys
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium E.E.Depart KU Leuven,Kasteelpark Arenberg 10,B-3001 Leuven,Belgium Intel assignee at IMEC
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
211-214
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）