Estimation of process variation impact on DG-FinFET Device performance using Plackett-Burman Design of Ezperiment Method

摘要：

This paper studies various Double-Gate (DG) FinFET structures optimized for better off state and on state performance. In this work,we study the impact of process variation on the performance of DG-FinFET device with 20nm gate length. This was achieved through calibrated TCAD simulations.We show that the spacer thickness variation has the highest impact on Ion,of the DG-FinFETs. In this work,we also have demonstrated the suitability of method of Plackett-Burman Design of Experiments (PB-DOE),for accurate estimation of the impact of the large number of process parameter-variations on DG-FinFET devices electrical performance.

作者: A.N.Chandorkar Sudhakar Mande Hiroshi Iwai

作者单位: Department of Electrical Engineering,Indian Institute of Technology Bombay,Powai,Mumbai -400076,Indi Frontier Collaborative Research Center,Tokoyo Institute of Technology,4259,Nagatsuta,Midori-Ku,Japan

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 215-218

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）