A Conduction Model for Intrinsic Polycrystalline Silicon Thin-Film Transistor Based on Energy-Dispersed Trap States at Discrete Grain Boundary
A quasi two-dimensional conduction model based on the thermionic emission of charge carriers over the energy barriers at discrete grain boundaries is proposed. The grain boundaries are characterized by an energy-dispersed density of trap states and a conduction model is formulated for a polycrystalline silicon thin-film transistor with an intrinsic channel.A line charge is formed adjacent to the interface of the channel and gate dielectric of the transistor by the occupied trap states and the electrostatic potential of a grain boundary is subsequently determined. This general approach allows the modeling of energy barriers for a transistor with an intrinsic channel and the resulting conduction model is continuously applicable from the pseudo sub-threshold to the linear regime of operation of a transistor.
Man Wong Thomas Chow Chun Cheong Wong Dongli Zhang
Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Clear Water Bay,Kowloon,Hong Kong
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
272-275
2008-10-20(万方平台首次上网日期,不代表论文的发表时间)