A Novel ESD Protection Circuit Applied in High-speed CMOS IC

摘要：

A new electrostatic discharge (ESD) protection circuit based on a standard of 0.6pm CMOS p-well technology has been designed and fabricated according to the request of trigger voltage,chip area and static current to high-speed CMOS IC. The new protection circuit was verified by a multi-project wafer (MPW) fabrication and tested by the transmission line pulse (TLP) generator system. The results show that new ESD protection circuit has lower trigger voltage,smaller chip area and a higher ESD failure voltage compared with those of gate grounded NMOS (ggNMOS) protection circuits with the same MPW. The voltage up to 5KV under human-body mode (HBM) test has been obtained.

作者: Bing Zhang Changchun Chai Yintang Yang

作者单位: Key Laboratory of Ministry of Education for Wide Band-gap Semiconductor Materials and Devices School of Microelectronics,Xidian University,Xian 710071,P.R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 345-348

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）