Modeling the gate current 1/f noise and its application to advanced CMOS devices

摘要：

In this work we propose an analytical model for the gate current 1/f noise in CMOS devices. The model is based on a simple idea: one electron trapped in the dielectric switches-off the tunneling through the oxide over an effective blocking area. The model allows evaluating the effective trap density inside the gate dielectric as a function of energy from measurements of the gate current 1/f noise versus gate voltage. Experimental data on advanced CMOS devices confirm the validity and the usefulness of the proposed model.

作者: F.Crupi P.Magnone G.Iannaccone G.Giusi C.Pace E.Simoen C.Claeys

作者单位: DEIS,University of Calabria,Via P.Bucci 41C,I-87036 Arcavacata di Rende (CS),Italy DIIEIT,University of Pisa,Italy IMEC,Leuven,Belgium IMEC,Leuven,Belgium E.E.Dept.,KU Leuven,Belgium

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 420-423

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）