Impact of NBTI on the Performance of 35nm CMOS Digital Circuits

摘要：

The negative bias temperature instability (NBTI) of p-MOSFET has the greatest impact on the long term reliability of nano-scale devices and circuits. For several decades,NBTI research has been focused at the device physics level or on the characterization methodology,with little attention paid to the impact of NBTI on the performance of basic digital circuits. This paper discusses the effects of NBTI on 35nm technology CMOS inverters and SRAM. The delay degradation and power dissipation of the inverters,as well as the static noise margin degradation of the SRAM are analysed. Moreover,the effects of power supply voltage on inverters and the cell ratio on SRAM under NBTI are also discussed.

关键词： Degradation inverters negative bias temperature instability (NBTI) SRAM static noise margin

作者: Yangang Wang M.Zwolinski

作者单位: School of Electronics and Computer Science,University of Southampton,Southampton,SO17 1BJ,UK

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 440-443

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）