Error Correction and Parasitics De-embedding for On-Wafer Transistor S-Parameter Measurements Using 4-Port Techniques
This paper presents the fundamentals and recent progresses of 4-port based error correction and parasitics de-embedding techniques we developed for high frequency transistor measurements. RF CMOS data from 2 to 110 GHz will be shown to illustrate various techniques.
Guofu Niu Xiaoyun Wei
Alabama Microelectronics Science and Technology Center Electrical and Computer Engineering Department 200 Broun Hall,Auburn University,Auburn,AL 36849 USA
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
472-475
2008-10-20(万方平台首次上网日期,不代表论文的发表时间)