Thermal Noise Performance in Recent CMOS Technologies
This paper reviews the measurement and modeling issues of the channel thermal noise in MOSFETs as a result of the aggressive reduction of the channel length into the sub-100 nm regimes. It also shows the noise performance of devices in 65 nm CMOS technology.
Chih-Hung Chen Bigchoug Hung Sheng-Yi Huang Jin-Shyong Jan Victor Liang Chune-Sin.Yeh
Electrical and Computer Engineering,McMaster University,Hamilton,Ontario,Canada United Microelectronics Corporation,Hsin-Chu,Taiwan,R.O.C United Microelectronics Corporation Group,Sunnyvale,CA,USA
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
476-479
2008-10-20(万方平台首次上网日期,不代表论文的发表时间)