High Performance MOSFET Scaling Study from Bulk 45 nm Technology Generation

摘要：

This paper presents a MOSFET scaling study based on the current 45 nm technology generation. The study is based on a real 35 nm gate length design,to which the simulation tools are carefully calibrates. Features such as strain enhancement,and high-κ/metal gates are included in the simulations,which then exhibit equivalent performance to state-of-the-art bulk devices. Realistic choices of device dimensions and doping profiles are made for the scaled devices,which indeed demonstrate the benefits from scaling and the introduction of technology boosters.

作者: Xingsheng Wang Scott Roy Asen Asenov

作者单位: Device Modelling Group,Department of Electronics and Electrical Engineering University of Glasgow,Glasgow G12 8LT,UK

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 484-487

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）