Wafer-Scale Processing of Aligned Carbon Nanotubes for Future Integrated Circuits

摘要：

We demonstrated essential technological components for wafer-scale integrated CMOS nanotube circuits such as inverters,NAND,and NOR logic gates: 1. The full-wafer-scale synthesis and transfer of massively aligned carbon nanotubes,and device fabrication on 4 inch substrates 2. In-depth device study and tuning,and extensive doping study for the first wafer-scale integrated CMOS nanotube circuits. 3. A novel device structure such as defect-tolerate logic gate.

作者: Chongwu Zhou

作者单位: Department of Electrical Engineering,University of Southern California,Los Angeles,CA90089,USA

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 537-540

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）