Comprehensive Study of Bias Temperature Instability on Polycrystalline Silicon Thin-Film Transistors
The negative and positive bias temperature instabilities are investigated on p-channel and n-channel TFTs with four different combinations. The stress-induced hump in the subthreshold region is observed for PBTI on p-channel TFTs and NBTI on n-channel TFTs. The hump is attributed to the edge transistors along the channel width direction. Higher electric field at the corners induces more trapped carriers in the insulator as compared to channel transistor. In contrast,no humps are observed for NBTI on p-channel TFTs and PBTI on n-channel TFTs. For NBTI on p-channel TFTs,the interface traps are generated by breaking the Si-H bonds and are responsible for the negative ΔVT. On the other hand,electrons are trapped in the insulator and induce positive ΔVT for PBTI on n-channel TFTs.
C.-F.Huang Y.-T.Chen H.-C.Sun C.W.Liu Y.-C.Hsu C.-C.Shin K.-C.Lin J.-S.Chen
Department of Electrical Engineering and Graduate Institute of Electronics Engineering,National Taiw AU Optronics Corp.,Hsinchu,Taiwan
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
624-627
2008-10-20(万方平台首次上网日期,不代表论文的发表时间)