Design Trends and Challenges of Logic Soft Errors in Future Nanotechnologies Circuits Reliability

摘要：

Nanometer circuits are becoming increasingly susceptible to soft errors due to alpha particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply voltage scaling reduces noise margins. The result is a significantly reduced reliability that becomes unacceptable in an increasingly number of applications as we move deeper to the nanotechnologies. In this context,logic soft errors,a concern for space applications in the past are a reliability issue at ground-level today. More and more techniques were used to mitigate various faults including the logic soft errors. The paper comprehensively analyzes logic soft errors sensitivity in future deep submicron processes,and also discusses the fault tolerant schemes at different design levels.

关键词： Nanometer Logic soft error Fault tolerant

作者: Hai Yu FAN Xiaoya Michael Nicolaidis

作者单位: TIMALaboratory,Grenoble,38031,France Northwestern Polytechnical University,Xian,710072,China Northwestern Polytechnical University,Xian,710072,China TIMALaboratory,Grenoble,38031,France iROC technologies

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 651-654

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）