Current Status and Possibilities of Wafer-Bonding-Based SOI Technology in 45nm or below CMOS LSIs

摘要：

The current status of SOI technology using wafer bonding is reviewed and its technological positioning in CMOS scaling is discussed. While bulk CMOS technology is encountering various kinds of critical issues,SOI technology using wafer bonding provides unique solutions by virtue of its flexible material design. Mobility enhancement through strained-SOI (sSOI) or optimization of crystal orientation (HOT,DSB),dynamic threshold voltage control by back-biasing (UT-BOX SOI),capacitor-less DRAM,etc.,are promising options that can bring a breakthrough and continue proper scaling. Also,circuit layer transfer technology applied to back-side illumination of CMOS imager is presented,as a technology giving linkage with future 3D-integration of LSI system.

作者: Makoto Yoshimi Daniel Delpra Ian Cayrefourcq George Celler Carlos Mazure Bernard Aspar

作者单位: Soitec Asia,Inc.3-3-1,Shin-Tokyo Building,Marunouchi,Chiyoda-ku,Tokyo,100-0005,Japan Soitec,Pare technologique des Fontaines,Bernin 38926,Crolles,Cedex,France Soitec USA,2 Centennial Drive,Peabody,MA 01960,USA

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 669-672

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）