Cell Devices for High-Density Flash Memory
By utilizing the fringing electric field from the control gate of cells in NAND flash memory string, the source/drain in the cells could be removed, which improves cell scalability and gives very positive effects. In this scheme, cells with underlapped S/D or localized buried oxide in the space shown more reasonable read current characteristics. For NOR flash memory, cells with recess channel structure have studied. We demonstrated successful operation of 4-bit/cell using the recess structure and found no interference in a cell and adjacent cells. Finally, we compared measured RTN in FinFET SONOS and saddle SONOS devices. The current fluctuation of the FinFET devices is higher by ～3 times than that in the saddle devices. We expect that our approach is very promising for future high density and high performance flash memory technology.
Jong-Ho Lee Young Min Kim Sung-Ho Bae Kyung-Rok Han I1-Hwan Cho
School of EECS,Kyungpook National University 1370 Sankyuk-Dong,Buk-Gu,Daegu,702-701 Korea Dept.of EE,College of Eng.,San38-2 Nam-Dong,Cheoin-Gu,Yongin-Si,Gyeonggi-Do,449-728,Korea
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
819-822
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）