Scaling of Stacked Gate Technology for embedded NVM

摘要：

Scaling limitations on NVM Stacked gate embedded into High-Performance (HP) CMOS logic process will be reviewed with potential solutions identified. As technology continues its shrink path into 65nm and beyond,scaling is becoming challenged due to the required high fields for write and erase (W/E) in stacked gate technology and the low leakage requirements for long term retention after cycling (RAC) problems. These requirements are imposing fundamental scaling limitations on the cell design as well as dielectrics thicknesses. These challenges require novel innovations to overcome and extend the viability of stacked gate technology to at least the 45nm node.

作者: D.Shum R.Kakoschke R.Strenz

作者单位: Infineon Technologies Dresden GmbH & Co.OHG Infineon Technologies AG,Munich,Germany

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 827-830

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）