A Novel Floating Gate Engineering Technique for Improved Data Retention of Flash Memory Devices
We propose one novel approach on engineering floating gate (FG) of Flash memory cell: carbon incorporation into polysilicon FG. This technique demonstrated improvement in retention and larger program/erase Vth,window,especially for smaller capacitance coupling ratio cell which is important for future scaled Flash memory cells.
Jing Pu Daniel S.H.Chan Byung Jin Cho
Department of ECE,National University of Singapore,Singapore 117576 Department of EECS,KAIST,335 Science Road,Yuseong,DaeJeon,Korea 305-701
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
839-842
2008-10-20(万方平台首次上网日期,不代表论文的发表时间)