Development of three-dimensional MOS structures from trench-capacitor DRAM cell to pillar-type transistor

摘要：

The author invented a trench-capacitor dynamic-random-access memory (DRAM) cell and applied the Japanese patent in 1975. The first trial development of trench-capacitor DRAM cell was presented in 1982 in 1-Mbit DRAM era. This might be the first attempt to utilize vertical wall of silicon substrate for metal-oxide-semiconductor(MOS) structure. Subsequent to this trial various kinds of vertical-channel MOS transistors have been proposed in integrated circuits field. This presentation will describe circumstances of invention and development of the trench-capacitor DRAM cell and subsequent development of several vertical-channel MOS transistors done by the authors group.

作者: Hideo Sunami

作者单位: Hiroshima University.Research Institute for Nanodevice and Bio Systems 1-4-2 Kagamiyama,Higashi-ruroshima.Hiroshima 739-8527,Japan

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 853-856

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）