A Novel Zero-Aware Read-Static-Noise-Margin-Free SRAM Cell for High Density and High Speed Cache Application

摘要：

To help overcome limits to the density and speed of conventional SRAMs,we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor SRAM cell using same design rules. Simulation result in standard 0.25μm CMOS technology shows purposed cell has correct operation during read/write and idle mode. The average delay of new cell is 20% smaller than a six-transistor SRAM cell.

作者: Arash Azizi Mazreah Mohammad Taghi Manzuri Shalmani Reza Noormandi Ali Mehrparvar

作者单位: Islamic Azad University, Sirjan Branch Sharif University of Technology

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 876-879

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）