Modeling and analysis of effect on bit-line voltage caused by imprint in FeRAM

摘要：

This study analyzed the effect on the bit-line voltage of imprint degradation in FeRAM. The hysteresis loop of the ferroelectric capacitor fitted by the three-line piecewise linear approximation model is proposed here to establish the relationship between bit-line voltage and imprint Formulas are derived from this model for approximately calculation of the variation of bit-line voltage along with imprint voltage. The results show a linear dependence of the bit-line voltage on the imprint,and the scope of this linear relationship are determined by the parameters extracted from the hysteresis loop. The results also show that the ferroelectric capacitor with a more rectangular hysteresis loop shows less variation of the bit-line voltage according to imprint.

关键词： modeling three-line piecewise imprint FeRAM

作者: Sheng-ze Zhou Ze Jia Tian-ling Ren

作者单位: Institute of Microelectronics,Tsinghua National Laboratory for Information Science and Technology,Tsinghua University,Beijing,China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 884-887

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）