Process challenges in CMOS FEOL for 32nm node

摘要：

With the navigation of ITRS,32nm technology node will be introduced around 2009. Scaling of CMOS devices from 45nm to 32nm node has come across significant barriers. In order to overcome these pitch-scaling induced barriers,it is demanded to integrate the most advanced process technologies into the product manufacturing. This paper will review and discuss new technology applications,which would be potentially integrated into the front end of line (FEOL) of 32nm node. Some examples are discussed in the following areas: double patterning,2 direct silicon bonding (DSB),hybrid orientation substrate technology,3 Metal/High-K (MHK) gate stacks,stress technologies and ultra-shallow junction (USJ).

作者: Guohua Wang Hanming Wu

作者单位: Semiconductor Manufacturing International Corporation (SMIC),Beijing,100176,P R.China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1134-1137

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）