Yield Monitor for Embedded-SiGe Process Optimization

摘要：

If not yield optimized,embedded SiGe (eSiGe) processes with aggressive transistor performance enhancements could induce high SRAM standby current and single cell failures in SRAM,In order to optimize the yield of eSiGe process,a SRAM-layout-based test structure was identified. It has the advantage of being able to be tested after silicidation or first metal level,therefore can be used as an early monitor of yield degradation due to eSiGe and therefore an effective vehicle for optimization between yield and performance. Using this monitoring structure,an eSiGe process optimized for yield was developed which does not show additional yield loss due to eSiGe while retaining comparable performance enhancements.

作者: Xu Ouyang Shwu-Jen Jeng Ishtiaq Ahsan Andrew Waite Karl Barth Hasan M.Nayfeh Yunyu Wang

作者单位: IBM Semiconductor Research and Development Center,Hopewell Junction,NY 12533,USA Advanced Micro Devices,Inc.,Hopewell Junction,NY 12533,USA

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1142-1145

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）