A Novel,Low-Cost Deep Trench Decoupling Capacitor for High-Performance,Low-Power Bulk CMOS Applications

摘要：

We present an overview and electrical results for a novel deep trench decoupling capacitor. The process of this decoupling capacitor borrows from the regular embedded DRAM trench process,but with significant process simplification for decoupling use which provide reduced cost and reduced process cycle time. This capacitor can provide significant chip-level area savings,using only 1/8 silicon real estate to fabricate the same capacitance as standard planar gate oxide capacitors. Additionally,the trench decap demonstrates a dramatic improvement in leakage compared to standard planar gate oxide capacitors -as much as 105 improvement in leakage can be realized using trench decaps instead of conventional planar decap designs.

作者: Chengwen Pei Subramanian Iyer Roger Booth Herbert Ho Naoyoshi Kusaba Xi Li Mary Jane Brodsky Paul Parries Huiling Shang Rama Divakaruni

作者单位: IBM Semiconductor Research & Development Center,2070 Route 52,Hopewell Junction,NY 12533,USA

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1146-1149

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）