65nm Poly Gate Etch Challenges and Solutions

摘要：

This paper presents an overview of 65nm poly gate fabrication challenges emerged during the device performance & yield enhancement on 300mm wafer. The proposed solutions hinge on the improvement of some critical process parameters in 65nm gate etch such as,critical dimension uniformity (CDU),through-pitch etch bias (TPEB),line width roughness (LWR) and poly gate profile. More than 7% yield enhancement and improved Vmin (the minimum voltage at which the addressed device function correctly) distribution have been obtained with improved CDU&TPEB.

作者: Yi Huang Shan-Shan Du Hai-Yang Zhang Hai-Hua Chen Qiu-Hua Han Shih-Mou Chang

作者单位: Semiconductor Manufacturing International Corporation (SMIC),18 Zhang Jiang Rd,Pudong New Area,Shanghai 201203,China

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1166-1169

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）