Microfabrication of Through Silicon Vias (TSV) for 3D SiP
A microfabrication flow for Through Silicon Via (TSV),as one of the critical and enabling technologies for three Dimensional System in Packaging (3D SiP),is presented in this paper. We focus on several critical processing steps for TSV fabrication,including: via micromachining; deposition of via insulation,barrier,and Cu seed layer; Cu electroplating for via-fill Si DRIE (Deep Reactive Ion E0tching) methods are used for the microdrilling of vias. Copper electroplating techniques with Periodic Pulse Reverse (PPR) current and solutions made in-house,are investigated for the filling and metallization of vias. The initial results are demonstrated in this paper. Vias with diameter/space/depth of 40μm (or plus)/100μm/100μm,have been successfully formed and filled,which proves the effectiveness of our efforts,and have partially paved the way to a multilayer-stacking homogeneous/heterogeneous integration-in-a package.
3D SiP Through Silicon Via (TSV) copper electroplating Periodic Pulse Reverse (PPR)
Hongguang Liao Min Miao Xin Wan Yufeng Jin Liwei Zhao Bohan Li Yuhui Zhu Xin Sun
National Key Laboratory on Micro/Nano Fabrication,Peking University,Beijing 100871,P.R.China National Key Laboratory on Micro/Nano Fabrication,Peking University,Beijing 100871,P.R.China Inst.Of National Key Laboratory on Micro/Nano Fabrication,Peking University,Beijing 100871,P.R.China Inst.of Inst.of Information Microsystem, Beijing Information Science & Technology Univ..Beijing 100085,P.R.C
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
1199-1202
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）