The Impact of Interface Quality on High-K Gate Dielectric Devices for 32 nm Technology and beyond

摘要：

Future devices will be fabricated with high-k/metal gate stack and possibly employ 3D devices and/or high mobility channel materials. Gate stack research targeted for devices scaled to 32nm and beyond should address the compatibility with scaled CMOS technologies in addition to the EOT scaling of High-K dielectric itself. This paper discusses recent progress and challenges in high-k dielectric for scaled CMOS technologies,especially the impact of the robustness of the interfacial layer beneath the high-K bulk on the MOSFET threshold voltage roll-off and the device reliability such as stress-induced leakage current (SILC). The directions to improve the interfacial quality of HK/MG stack will be discussed. Challenges of high-K dielectric formation targeted for future SiGe channel devices will be highlighted.

作者: Hsing-Huang Tseng

作者单位: Front End Processes Division,SEMATECH,Austin,Texas,USA

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1245-1248

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）