Interface Engineering for High-k/Ge Gate Stack

摘要：

In this paper,various interface engineering techniques for high-k/Ge gate stack for advanced CMOS device applications are reviewed. High-k gate stack formation on Ge substrate is first addressed with emphasis on pre-gate surface passivation. Post gate dielectric (post-gate) treatments are then discussed to further improve the high-k/Ge interface quality.

作者: Ruilong Xie Chunxiang Zhu

作者单位: Silicon Nano Device Laboratory (SNDL),Department of Electrical and Computer Engineering National Uni Silicon Nano Device Laboratory(SNDL),Department of Electrical and Computer Engineering National Univ

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1252-1255

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）