Integrate LaOz-capping layer into metal gated CMOS devices using a gate-first approach for sub-45nm technology node and the device reliability thereof

摘要：

This paper provides a comprehensive study on the integration of LaOx capping layer for sub-45nm metal gated CMOS devices with Hf-based high-K dielectrics in a gate first manner. Two different integration routes,i.e. Dual Metal Dual Dielectric flow (DMDD) and Single Metal Dual Dielectric (SMDD) flow,are reported and compared. The device reliability study is also provided.

作者: Hong Yu Yu S.Z Chang S.Kubicek T.Schram X.P.Wang S.Biesemans

作者单位: School of EEE,Nanyang Technological University,Singapore 639798 IMEC,B-3001 Leuven,Belgium TSMC assignee to IMEC IMEC,B-3001 Leuven,Belgium

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1260-1263

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）