TCAD Application in Process Optimization to Reduce Source/Drain Junction Capacitance of PMOS Transistor in the Development of 65nm Low Leakage Technology
In this paper,technology computer aided design (TCAD) was applied to optimize the fabrication process to reduce the parasitic capacitance of PMOS transistor at the source/drian (S/D) junction (Cj) in developing the 65nm low leakage (65nmLL) technology. It was found that Cj can be effectively reduced by combining relative high-energy well implant and proper threshold voltage (Vt) implant method. Through measured data and TCAD simulation,this paper also demonstrates a doping compensation effect by tuning Vt and Halo implants with proper species,energy,and dosage,to achieve the Cj reduction.
Xuejie Shi Scott Lee Haohua Ye Jianhua Ju Waisum Wong
Semiconductor Manufacturing International Corporation,#18,Zhang Jiang Road,Shang Hai 201203,P.R.China
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
1328-1331
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）