THREE-DIMENSIONAL IMPEDANCE ENGINEERING FOR MIXED-SIGNAL SYSTEM-ON-CHIP APPLICATIONS

摘要：

We describe a novel approach for three-dimensional substrate impedance engineering using p-/p+epi substrate for mixed-signal SoC applications. Highly doped substrate with a thin epitaxial layer is used to prevent latch-up at tight design rules in high performance digital CMOS for beyond 40 GHz applications. Metal vias extending from the chip surface to the p+substrate are used as Faraday cage for EM wave shielding as well as true ground contacts. Self-limiting semi-insulating mciro-PS regions are iaserted into selected regions of Si substrates from the backside of the wafer. On-chip inductors are situated above the semi-insulating micro-PS regions allowing for greatly increased Q and fr. Bond pads on micro-PS regions increase the bond pad resonant frequency of up to 56.2 GHz and increase crosstalk isolation between bond pads. These technologies require minimum intrusion to conventional Si CMOS processing,making them practical and yet effective new technologies that offer outstanding improvements with regard to the performance of mixed-signal SoCs. It is an enabling factor for Si ICs to directly challenge the compound semiconductor technologies.

作者: Kyuchul Chong Ya-Hong Xie

作者单位: Department of Materials Science and Engineering,University of California,Los Angles,Los Angeles,CA 90095,USA

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1447-1451

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）