Design optimization of a 10 GHz Low Noise Amplifier with gate drain capacitance consideration in 65 nm CMOS Technology

摘要：

Most of papers have ignored the effect of gate-drain capacitance of transistor due to its complexity when they analyze a low noise amplifier circuit (LNA). However,as scaling down the CMOS technology,the ratio of gate-drain capacitance (Cgd) to gate-source capacitance (Cgs) increases. This phenomenon affects the input matching,power gain and noise figure of the LNA circuit. In this paper,we propose the circuit analysis with new analytic equations derived from equivalent circuit of LNA which considered the Cgd effect. With this approach,the input power matching,overall trans-conductance and noise figure could be accurately calculated more than conventional equation.Moreover,a design approach is introduced to optimize the LNA circuit. Prior to fabrication of full LNA circuit,optimum bias and width could be determined to maximize FoM. This paper shows the guide line to design an LNA circuit at 10 GHz operating frequency using 65 nm technology.

作者: Hakchul Jung Hee-Sauk Jhon Ickhyun Song Minsuk Koo Hyungcheol Shin

作者单位: School of Electrical Engineering and Computer Science.Inter-University Semiconductor Research Center School of Electrical Engineering and Computer Science.Inter-University Semiconductor Research Center School of Electrical Engineering and Computer Science.Inter-University Semiconductor Research Center

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1480-1483

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）