A 2.4 GHz CMOS Ultra Low Power Low Noise Amplifier Design with 65 nm CMOS Technology

摘要：

In this paper,design approach of 2.4 GHz CMOS ultra low power Low Noise Amplifier (LNA) using 65 nm CMOS technology is presented. Conventional Inducti -vely degenerated cascode topology where both MOS transistors are biased in sub-threshold region is used. There are many performance factors of LNAs such as signal power gain,noise factor,input referred 1-dB compression point (P(-1)dBin) and power consumption. In low power design,above all things proper power gain and low power consumption should be attained. This limitation makes ultra low power LNA optimization different from ordinary one. We analyze each perfor -mance factor in low power design and optimize figure of merit (FoM) with some specification goal.

作者: MinSuk Koo Hakchul Jung Ickhyun Song Hee-Sauk Jhon Hyungcheol Shin

作者单位: School of Electrical Engineering and Computer Science,Seoul Nat1 Univ.Seoul,Korea

会议类型: 国际会议

会议名称: 9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)

会议地点: 北京

会议语种:英文

页码: 1488-1491

在线出版日期: 2008-10-20（万方平台首次上网日期，不代表论文的发表时间）