A Dual Loop Dual VCO CMOS PLL Using a Novel Coarse Tuning Technique for DTV
A CMOS phase-locked loop (PLL) which synthesizes frequencies between 474 and 858 MHz in steps of 1MHz and settles in less than 180μs is presented. This PLL can be implemented as a sub-circuit for a frequency synthesizer which serves for UHF Digital-TV receiver. To realize fast loop settling,integer-N architecture that work with 1 MHz reference frequency is implemented and a novel adaptive frequency calibration (AFC) of programmable dichotomizing coarse tuning technology is integrated. The novel AFC structure uses pulses of 2n times of the PFDs reference frequency for counting and comparison. Two multi-band voltage controlled oscillators,which cover 866 to 1468 MHz and 1282 to 1892 MHz separately,are implemented so as to reduce VCO output noise and power consumption by reducing VCO gain on each frequency turning curse. I/Q carriers are generated by VCO output divided by 2. Fabricated in 0.18-μm CMOS technology,the PLL achieves phase noise of less than -132dBc/Hz at 1.45 MHz offset.
phase-locked loops adaptive frequency calibration dual VCO phase noise dual loop
Congyin Shi Huaizhou Yang Huiling Xiao Junhua Liu Huailin Liao
Key Laboratory of Microelectronic Devices and Circuits,Institute of Microelectronics,Peking University,Beijing 100871,P.R.China
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
1597-1600
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）