A Novel Pipelined CCK Decoder for IEEE 802.11b System
A novel decoder for Complementary Code Keying (CCK) modulation is proposed in this work. Compared to the parallel decoder architecture based on Fast Walsh Transform (FWT),the presented pipelined architecture has better hardware sharing and utilization efficiency,as well as smaller area. Its hardware area for finding the maximum decoding output value is minimized by employing a low-complexity on-the-fly comparator that takes advantage of the sequentially incoming chips and the pipelined data flow. Also,the proposed design consumes only 50.6 μw at 11MHz based on UMC 0.18-μm process,which is much lower than the conventional FWT-based architecture. Thus it is a low-power and lowarea solution for the design of a high-performance 802.11b system.
Shen-Rei Huang Sau-Gee Chen
Department of Electronics Engineering and Institute of Electronics,National Chiao Tung University 1001 Ta-Hsueh Road Hsinchu,Taiwan
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
1621-1624
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）