A 5.6-mW Power Dissipation CMOS Frequency Synthesizer for L1/L2 Dual-Band GPS Application
This paper presents a wide tuning range CMOS frequency synthesizer for dual-band GPS receiver which has been fabricated in a standard 0.18-um RF CMOS process. With a high Q on-chip inductor,the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45GHz and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8mA to 0.4mA,from a 1.8V supply voltage. The measurement results show that the whole frequency synthesizer costs a very low power consumption of 5.6mW working at L1 band with in-band phase noise less than -82dBc/Hz and out-of-band phase noise about -112 dBc/Hz at 1MHz offset from a 3.142GHz carrier.
PLL GPS Frequency Synthesizer VCO Low Power CMOS RF Phase Noise Charge Pump
Hailong Jia Tong Ren Min Lin Fangxiong Chen Yin Shi Foster F.Dai
Institute of Semiconductors Chinese Academy of Sciences Beijing 100083,China Department of Electrical & Computer Engineering Auburn University Auburn,Alabama 36849,USA
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
1637-1640
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）