Fully Automated Physical Implementation Methodology for Tolapai-The First IA Based SoC
The integration of todays complex multi-power domain IOs,inherited from legacy Reuse IP sources,poses a big challenge to the full chip physical integration in terms of product cost and design cycle time for products such as Tolapai,the first IA based SoC with IA CPU core,South Bridge (ICH),North Bridge (MCH),acceleration hardware and networking interfaces. To meet these challenges,the Tolapai design team created the IntelR first fully automated physical implementation methodology that accomplished a 28 percent reduction in the final design convergence cycle from RTL freeze to tape-out with about 20 percent fewer design resources over the entire project. The methodology features a fully automated ASIC implementation method for integrating multi-power well IO blocks,high speed block,and a Correct by Construction solution for the deep sub-micron technology challenges such as strict via density and double via rule on the wide metal without introducing new DRC violations. The automation provides quick turn-around of the several iterations required to achieve performance verification and final conveigence while requiring no mask design resources.
Yuyun Liao Gaurav Mehta Ming-Xu Liu Yu-chieh Su Nishi Raman
Intel Corporation,Chandler,AZ 85226,USA
国际会议
9th International Conference on Solid-State and Integrated-Circuit Technology(第9届固态和集成电路国际会议)
北京
英文
1815-1818
2008-10-20（万方平台首次上网日期，不代表论文的发表时间）